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The testbench structure is shown in Figure 8-2 . It instantiates a single core that is connected to the PCI bus. The core is
instantiated in the PCISYSTEM module. This adds backend memory and FIFOs to the core to create a simple PCI
system.
PCI
Monitor
PCISYSTEM
CorePCIF
Bar 0
Memory
Bar 1
FIFO
Bar 1
Simple
PCI Target
Target = 1
Master = 1
Backend = 1
FIFO
Backend
Control
PCI
Master
Procedural Testbench
Figure 8-2 · User Testbench
Also attached to the PCI bus are a PCI monitor that displays the PCI bus activity and a simple PCI Target model that is
used as a Target when CorePCIF is carrying out DMA activity. The PCI Master module is used by the procedural
testbench to carry out PCI cycles. The procedural testbench can also access the CorePCIF backend interface to program
the DMA registers.
The PCISYSTEM module creates a simple PCI system that contains a memory BAR and a second BAR connected to
input and output FIFOs. Data from the output FIFO is moved to the input FIFO at a variable rate controlled by the
procedural testbench.
The PCISYSTEM design can be synthesized when the Axcelerator, IGLOO/e, ProASIC3/E, or Fusion FPGA family
is selected, creating a single-chip PCI system. To synthesize the design, move the pcisystem , fifo , memory , fifo512x32 , and
ram2k8 files from the CorePCI stimulus directory to the HDL source files directory in Libero IDE. Also supplied is an
even simpler design, PCISYSTEM2, that implements just a memory BAR connected to the PCI core. This can be
synthesized by copying the pcisystem2 file as well.
122
v4.0
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